The present invention generally relates to a semiconductor integrated circuit having a CMOS (complementary metal oxide semiconductor) inverter, and particularly to the suppression of a ringing noise which causes a malfunction of a semiconductor integrated circuit having a CMOS inverter.
Currently, there is a trend on increase in the integration level and operational speed of a CMOS transistor circuit. Additionally, a high-speed or high mutal transconductance CMOS buffer becomes available. Such a CMOS buffer is frequently used to form an output buffer. As is well known, a ringing noise is a serious problem which frequently occurs in a high-speed or high-driveability CMOS output buffer. Particularly, a ringing noise causes a level inversion when an output signal of a circuit having a CMOS inverter falls.
Referring to FIG. 1, a ringing noise is interposed on an output waveform (b) of a CMOS inverter when an input signal (a) is applied thereto. As is illustrated, the output waveform alternately changes due to the presence of the ringing noise. Generally, the low threshold potential of a CMOS inverter is set equal to approximately 1.5 volts, when a TTL interface is used. Alternatively, the low threshold potential is set equal to approximately 2.5 volts, when a high-potential power source voltage V.sub.DD is set equal to 5 volts and a low-potential power source voltage V.sub.SS is set equal to 0 volt. Therefore, when the output signal falls, the level of the output signal may be alternately inverted. Also, the potential (c) of a ground terminal (a V.sub.SS terminal) of the CMOS buffer changes depending on the change of the output waveform. If a ringing noise is introduced into a bus, for example, it may affect an internal circuit formed in an LSI circuit and causes a malfunction thereof. The reason why ringing frequently occurs in a CMOS circuit is as follows. First, the output waveform changes in a full swing of the power source voltage, between 5 volts to 0 volt, for example. Secondly, a current passes through the CMOS inverter at a dash, and additionally there is no branch path through which the current passes. Particularly, the occurrence of ringing noises described above is a serious problem in aiming to increase the operational speed of MOS transistors.
FIG. 2 illustrates a conventional CMOS output buffer provided with no measurement to count a ringing noise. An output buffer 1 consists of two cascaded CMOS inverters 4 and 7. The CMOS inverter 4 is made up of a P-channel MOS transistor (hereinafter simply referred to as a PMOS transistor) 2 and an N-channel MOS transistor (hereinafter simply referred to as an NMOS transistor) 3. Similarly, the CMOS inverter 7 is made up of a PMOS transistor 5 and an NMOS transistor 6. A variation in the output signal supplied from the output buffer 1 as a function of time is illustrated by a broken line shown in FIG. 5. It can be seen from FIG. 5 that the output signal decreases to ground level rapidly. This rapid decrease of the output signal causes a ringing noise.
FIG. 3 illustrates a configuration of a conventional low-noise type CMOS output buffer 8 equipped with a ringing noise reduction circuit. An input signal Vin is applied to input inverters 9 and 10. The input inverter 9 is made up of a PMOS transistor 11, and NMOS transistors 12 through 15. The gates of the NMOS transistor 13 through 15 connected in series are connected to a high-potential power source V.sub.DD. The source of the NMOS transistor 15 is connected to a low-potential power source V.sub.SS. The input inverter 10 is made up of PMOS transistors 16, and 18 through 20, and an NMOS transistor 17. The gates of the PMOS transistors 18 through 20 connected in series are connected to the low-potential power source V.sub.SS. The source of the NMOS transistor 17 is connected to the low-potential power source V.sub.SS. The source of the PMOS transistor 18 is connected to the high-potential power source V.sub.DD. The output signal of the input inverter 9 is supplied to the gate of a PMOS transistor 22, which is a part of an output inverter 21. The output signal of the input inverter 10 is supplied to the gate of an NMOS transistor 23, which is another part of the output inverter 21.
The potential of the source of the NMOS transistor 12 is pulled up to a potential V.sub.SS, due to the presence of the NMOS transistors 13 through 15 (V.sub.SS' &gt;V.sub.SS). The potential of the drain of the PMOS transistor 16 is pulled down to a potential V.sub.DD, due to the presence of the PMOS transistors 18 through 20 (V.sub.DD &gt;V.sub.DD'). Therefore, when the input signal Vin is changed from "L (low level)" to "H" (high level)", the NMOS transistor 12 is not turned ON until the NMOS transistor 12 is supplied with a threshold voltage higher than a normal threshold voltage obtained in case where the CMOS inverter 9 consists of the PMOS and NMOS transistors 11 and 12. This is because the threshold voltage of the NMOS transistor 12 is set so as to be shifted toward the V.sub.DD level. Thereafter, when the input signal Vin exceeds the threshold voltage of the NMOS transistor 12 which is higher than the normal threshold voltage, the NMOS transistor 12 is turned ON and the PMOS transistor 11 is turned OFF. Then the gate of the PMOS transistor 22 becomes equal to the potential V.sub.SS', and thus the PMOS transistor 22 is turned ON. As a result, an output signal Vout becomes equal to the potential V.sub.DD.
On the other hand, when the input signal Vin is changed from "H" to "L", the PMOS transistor 16 is not turned ON until the PMOS transistor 16 is supplied with a threshold voltage lower than a normal threshold voltage obtained in case where the CMOS inverter 10 consists of the PMOS and NMOS transistors 16 and 17. Then when the input signal Vin becomes equal to the threshold voltage of the PMOS transistor 16 which is lower than the normal threshold voltage, the PMOS transistor 16 is turned ON and the NMOS transistor 17 is turned OFF. Therefore, the gate of the NMOS transistor 23 becomes equal to the potential V.sub.DD'. As a result, the output signal Vout becomes the potential V.sub.SS. In this manner, the improvement of FIG. 3 reduces a time during which both the PMOS and NMOS transistors 22 and 23 are ON, and thereby reduces a through current passing therethrough. The waveform of the output signal Vout at the output inverter 21 is illustrated as a solid line C1 shown in FIG. 5. It can be seen from FIG. 5 that the output signal available in the output buffer 8 decreases slowly, compared with the output signal available in the output buffer 1 shown in FIG. 2.
However, the output buffer 8 having the conventional ringing noise reduction circuit shown in FIG. 3 has the following disadvantages to be overcome. As described above, the ringing noise is reduced by slowly decreasing the output signal Vout as indicated by the curve C1. However, the above causes an increase of the response time of the output signal Vout, and thus prevents the output buffer 8 from operating with high speeds. In other words, the output buffer 8 does not satisfy high-speed operation and small ringing noise at the same time.